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| MOSEL VITELIC INC. Preliminary MV20556 8 - Bit MCU Mouse Controller Bit operation instructions Page free jumps 8 - bit Unsigned Division 8 - bit Unsigned Multiply BCD arithmatic Direct Addressing Indirect Addressing Nested Interrupt Two priority level interrupt A full duplex serial I/O port Working at 16/25/40 MHz Clock Full static operation: 3 MHz through 16 MHz July 1997 Features General 8051 instruction family compatible Operate at voltage 5.0V. No External Memory is supported 8 bit bus I/O ports 4 K byte ROM 128 byte RAM 128 byte depth stack Two 16 bit Timers (Event Counters) 15 programmable I/O pins Five interrupt sources Programmable serial UART channel Direct LED drive output Description The MVI MV20556 is an 8 - bit single chip microcontroller. It provides hardware features and powerful instruction set that are necessary to make it a versatile and cost effective controller for mouse applications which needs up to 4K byte internal memory either for program or for data and mixed. A serial input / output port is provided for I/O expansion, Inter - processor communications, full duplex UART. Pin Configuration RES RXD/P 3.0 TXD/P 3.1 XTA2 XTAL1 #INT0/P 3.2 #INT1/P 3.3 T0/P 3.4 1 2 3 4 5 6 7 8 9 10 20 19 VDD P 1.7 P 1.6 P 1.5 P 1.4 P 1.3 P 1.2 P 1.1 P 1.0 P 3.7 MV20556 20L PDIP 300 mil (Top View) 20L SOP (Top View) 18 17 16 15 14 13 12 11 Ordering Information MV20556ajk - pqrs a: process identifier. { C:=COMS } jk: working clock in MHz. { 16 } pqr: production code { 001, ..., 999 } s: package type. { P: 20L 300 mil PDIP } Pin/Pad Postfix blank N S Package dice 20L PDIP 20L SOP Configuration page 25 page 1 page 1 Dimension page 25 page 23 page 24 T1/P 3.5 VSS Logo Size at Top Marking 4.5 x 3.8 mm 4.0 x 3.4 mm Specifications subject to change without notice, contact your sales representatives for the most recent information. 1/27 PID256** 07/97 MOSEL VITELIC INC. Preliminary MV20556 Block Diagram Decoder & Register 128 bytes RAM 4K bytes ROM Timer 1 Timer 0 Stack Pointer RES Reset Circuit to pertinent blocks to whole chip Vdd Vss Power Circuit Buffer2 Interrupt Circuit to pertinent blocks 128 bits SFR includes Acc & PSW, etc. Register Buffer Buffer1 DPTR ALU PC Increamenter XTAL2 XTAL1 Timming Generator to whole system Program Counter Port 3 Latch Port 1 Latch Port 3 Driver Port 1 Driver 7 8 Specifications subject to change without notice, contact your sales representatives for the most recent information. 2/27 PID256** 07/97 MOSEL VITELIC INC. Preliminary MV20556 Pin Descriptions 20L PDIP Pin# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 20L SOP Pin# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Pad# 4 5 6 7 8 9 10 11 12 13-15 17 18 19 20 21 22 23 24 1 2, 3 RES RXD/P3.0 TXD/P3.1 XTAL2 XTAL1 #INT0/P3.2 #INT1/P3.3 T0/P3.4 T1/P3.5 VSS P3.7 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 VDD L/L/i i/o i/o i o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o Reset bit 0 of Port 3 & Receive data bit 1 of Port 3 & Transmit data Crystal out Crystal in bit 2 of Port 3 & low true Interrupt 0 bit 3 of Port 3 & low true Interrupt 1 bit 4 of Port 3 & external input to Timer 0 bit 5 of Port 3 & external input to Timer 1 Sink Voltage, Ground bit 7 of Port 3 bit 0 of Port 1 bit 1 of Port 1 bit 2 of Port 1 bit 3 of Port 1 bit 4 of Port 1 bit 5 of Port 1 bit 6 of Port 1 bit 7 of Port 1 Drive Voltage, +5 Vcc dice Symbol Active I/O Names Signal Descriptions Vss Circuit ground potential. VDD +5V power supply during operation. PORT 1 Port 1 is an 8-bit quasi-bidirectional I/O port. There is a pull-up resistance when operating at either input or output. PORT 3 Port 3 is an 7-bit quasi-bidirectinal I/O port. It also contains the interrupt and timer as well as serial port pins that are used by various options. The output latch corresponding to a secondary function must be programmed to one (1) for that function to operate. The secondary functions are assigned to the pins of port 3, as follows: - RXD/data (P3.0). Serial port's transmitter data input (asynchronous) or data input/output (asynchronous). - TXD/clock (P3.1). Serial port's transmitter data output (asynchronous) or data input/output (asynchronous). - #INT0 (P3.2). Interrupt 0 input or gate control input for counter 0. - #INT1 (P3.3). Interrupt 1 input or gate control input for counter 1. - T0 (P3.4). Input to counter 0. - T1 (P3.5). Input to counter 1. There is a pull-up resistance when operating at either input or output. RES A low to high transition on this pin (V IH1) while the oscillator is not running resets the MV20556. Holding high signal (higher than V IH1) on this pin for two machine cycles (24 clocks) or longer while the oscillator is running, resets the device. XTAL 1 Input to the oscillator's high gain amplifier. A crystal or external source can be used. XTAL 2 Output from the oscillator's amplifier. Required when a crystal is used. Specifications subject to change without notice, contact your sales representatives for the most recent information. 3/27 PID256** 07/97 MOSEL VITELIC INC. Preliminary MV20556 Function Overall The CPU of MV20556 manipulates versatile operands in four memory spaces. They are 4 KB program ROM, 128-byte internal Data RAM, 20 SFRs and 16-bit program counter. The Internal Data Memory address space is further divided into the 128-byte Internal Data RAM and 128-byte Special Function Register (SFR) address spaces shown in latter Figures. Four Register Banks (each with eight registers), 128 addressable bits, and the stack reside in the Internal Data RAM. The stack depth is limited only by the available Internal Data RAM and its location is determined by the 8-bit Stack Pointer. All registers except the Program Counter and the four 8-Register Banks reside in the Special Function Register address space. These memory mapped registers include arithmetic registers, pointers, I/O ports, and registers for the interrupt system, timers and serial channel. 128 bit locations in the SFR address space are addressable as bits. The MV20556 contains 128 bytes of Internal Data RAM and 20 SFRs. The MV20556 provides a non-paged Program Memory address space to accommodate relocatable code. Conditional branches are performed relative to the Program Counter. The register-indirect jump permits branching relative to a 16-bit base register with an offset provided by an 8-bit index register. Sixteen-bit jumps and calls permit branching to any location in the contiguous 4K Program Memory address space. The MV20556 has five methods for addressing source operands: Register, Direct, Register-Indirect, Immediate, and Base-Register-plus Index-Registe -Indirect Addressing. The first three methods can be used for addressing destination operands. Most instructions have a "destination, source" field that specifies the data type, addressing methods and operands involved. For operations other than moves, the destination operand is also a source operand. Any register in the four 8-Register Banks can be accessed through Register, Direct, or Register-Indirect Addressing; the 128 bytes of Internal Data RAM through Direct or Register-Indirect Addressing; and the Special Function Registers through Direct Addressing. External Data Memory is accessed through Register-Indirect Addressing. Look-Up-Tables resident in Program Memory can be accessed through Base-Register-plus Index-Register-Indirect Addressing. The MV20556 is classified as an 8-bit machine since the internal ROM, RAM, Special Function Registers, Arithmetic/Logic Unit and external data bus are each 8 bits Specifications subject to change without notice, contact your sales representatives for the most recent information. wide. The MV20556 performs operation on bit, nibble, byte and double-byte data types. The MV20556 has extensive facilities for byte transfer, logic, and integer arithmetic operations. It excells at bit handling since data transfer, logic and conditional branch operantions can be performed directly on Boolean variables. 4/27 PID256** 07/97 MOSEL VITELIC INC. Preliminary MV20556 Memory Map Overall The CPU of MV20556 is able to access three memory areas. They are: (1) 128 bytes data RAM addressed at 00H through 7FH; (2) 20 SFRs addressed at 80H through FFH; (3) 4,096 bytes program ROM addressed at 000H through FFFH. Be noted, MCU MV20556 builds all accessible memory inside, it is unable to access external memory. 4095 FFFH 255 128 127 0 Internal Data RAM FFH 80H 7FH 00H 255 128 FFH F0H 0 Special Function Register Internal Program ROM 000H Internal Memory Map Specifications subject to change without notice, contact your sales representatives for the most recent information. 5/27 PID256** 07/97 MOSEL VITELIC INC. Preliminary MV20556 Memory Map Details Internal RAM The MV20556 contains a 128-byte Internal Data RAM (Which includes registers R7-R0 in each of four Banks), and twenty memory-mapped Special Function Registers. Internal Data RAM The Internal Data RAM provides a convenient 128-byte scratch pad memory. Register Banks There are four Register Banks within the Internal Data RAM. Each Register Bank contains registers R7-R0. 128 Addressable Bits There are 128 addressable software flags in the Internal Data RAM. They are located in the 16 byte locations starting at byte address 32 and ending with byte location 47 of the RAM address space. Stack The stack may be located anywhere within the Internal Data RAM address space. The stack may be as large as 128 bytes on the MV20556. 7Fh RAM BYTE (MSB) 7FH (LSB) 127 scratch pad area 2FH 2EH 2DH 2CH 2BH 2AH 29H 28H 27H 26H 25H 24H 23H 22H 21H 20H 1FH 18H 17H 10H 0FH 08H 07H 00H 7F 77 6F 67 5F 57 4F 47 3F 37 2F 27 1F 17 0F 07 7E 76 6E 66 5E 56 4E 46 3E 36 2E 26 1E 16 0E 06 7D 75 6D 65 5D 55 4D 45 3D 35 2D 25 1D 15 0D 05 7C 74 6C 64 5C 54 4C 44 3C 34 2C 24 1C 14 0C 04 7B 73 6B 63 5B 53 4B 43 3B 33 2B 23 1B 13 0B 03 7A 72 6A 62 5A 52 4A 42 3A 32 2A 22 1A 12 0A 02 79 71 69 61 59 51 49 41 39 31 29 21 19 11 09 01 78 70 68 60 58 50 48 40 38 30 28 20 18 10 08 00 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 23 24 16 15 8 7 0 30h 2Fh bit addressable area RS1 RS0 R7 11 R0 R7 10 R0 R7 01 R0 R7 00 R0 00h 08h 07h 10h 0Fh Four bank area 18h 17h 20h 1Fh Bank 3 Bank 2 Bank 1 Bank 0 128B RAM Bit Address Specifications subject to change without notice, contact your sales representatives for the most recent information. 128B RAM Memory Map 6/27 PID256** 07/97 MOSEL VITELIC INC. Preliminary MV20556 Memory Map Details (Cont'd) Special Function Registers (SFR) The Special Function Registers include arithmetic registers (Acc, B, PSW), pointers (SP, DPH, DPL) and registers that provide an interface between the CPU and the on-chip peripheral functions. These are also 128 addressable bits within the Special Function Registers. The memory-mapped locations of these registers and bits are shown in right side figure. Acc Register The Acc register is the accumulator. B Register The B register is dedicated during multiply and divide and serves as both a source and a destination. During all other operations the B register is simply another location of the Special Function Register space. Program Status Word Register The carry (CY), auxiliary carry (AC), user flag 0 (F0), register bank select (RS0 and RS1), overflow (OV) and parity (P) flags reside in the Program Status Word (PSW) Register. These flags are bit-memory-mapped within the byte-memory-mapped PSW. The PSW flags record processor status information and control the operation of the processor. The CY, AC, and OV flags generally reflect the status of the latest arithmetic operations. The P flag always reflects the parity of the Acc register. The carry flag is also the Boolean accumulator for bit operations. SYMBOLIC ADDRESS BIT ADDRESS BYTE ADDRESS 255 B 247 Acc 231 PSW 248 240 (F0H) 240 224 (E0H) 224 208 (D0H) Direct Byte Address (MSB) Bit Addresses Hardware Register (LSB) Symbol 215 IPC 191 208 184 (B8H) 184 176 (B0H) 240 F7 F6 F5 F4 F3 F2 F1 F0 B P3 183 176 224 E7 CY E6 AC D6 E5 FO D5 E4 RS1 D4 E3 RS0 D3 E2 OV D2 E1 E0 P Acc IEC 175 168 168 (A8H) 208 D7 D1 D0 PSW P2 167 160 160 (A0H) SFR's Containing Direct Addressable Bits PS 184 BC PT1 BB PX1 BA PT0 B9 PX0 B8 IP SBUF SCON 159 152 153 (99H) 152 (98H) 176 B7 EA B6 B5 B4 ES B3 ET1 AB B2 EX1 AA B1 ET0 A9 B0 EX0 A8 P3 P1 151 144 144 (90H) 168 AF - - AC IE TH1 TH0 141 (8DH) 140 (8CH) 139 (8BH) 138 (8AH) 137 (89H) 136 (88H) 143 136 131 (83H) 130 (82H) 129 (81H) 128 (80H) 135 128 160 A7 SM0 A6 SM1 9E A5 SM2 9D A4 REN 9C A3 TB8 9B A2 RB8 9A A1 TI 99 A0 RI 98 P2 TL1 TL0 152 9F SCON TMOD TCON 144 97 TF1 96 TR1 8E 95 TF0 8D 94 TR0 8C 93 IE1 8B 92 IT1 8A 91 IE0 89 90 IT0 88 P1 DPH TCON DPL SP 136 8F 128 87 86 85 84 83 82 81 80 P0 P0 SFR Bit Address Specifications subject to change without notice, contact your sales representatives for the most recent information. SFR Memory Map 7/27 PID256** 07/97 MOSEL VITELIC INC. Preliminary MV20556 Memory Map Details (Cont'd) Program Status Word Register(Cont'd) F0 is a general purpose flag which is pushed onto the stack as part of a PSW save. The two Register Bank select bits (RS1 or RS0) determine which one of the four Register Banks is selected. Stack Pointer The 8-bit Stack Pointer (SP) contains the address at which the last byte was pushed onto the stack. This is also the address of the next byte that will be popped. The SP is incremented during a push. SP can be read or written to under software control. Data Pointer (High) and Data Pointer (Low) The 16-bit Data Pointer (DPTR) register is the concatenation of registers DPH (data pointer's high-order byte) and DPL (data pointer's low-order byte). The DPTR is used in Register-Indirect Addressing to move Program Memory constants, to move External Data Memory variables, and to branch over the 64K Program Memory address space. Interrupt Priority Register The Interrupt Priority (IPC) register contains the control bits to set an interrupt to a desired level. A bit set to a one gives the particular interrupt a high priority listing. Interrupt Enable Register The Interrupt Enable (IEC) register stores the enable bits for each of the five interrupt sources. Also included is a global enable/disable bit of the interrupt system. Timer/Counter Mode Register Within the Times Mode (TMOD) register are the bits that select which operations each timer/counter will do. Timer/Counter Control Register The timer/counters are controlled by the Timer/Counter Control (TCON) register bits. The start/stop bits for the timer/counters along with the overflow and interrupt request flags are mapped in TCON. Timer/Counter 1 (High), Timer/Counter 1 (Low), Timer/Counter 0 (High), Timer/Counter 0 (Low) There are four register locations for the two 16-bit timer/counters. These registers can be read or written to, to give the programmer easy access to the timer/counters. TH1 and TH0 refer to the 8 high-order bits of timer/counter 1 and 0, respectively. TL1 and TL0 refer to the low-order bits of both timer/counter 1 and 0. Serial Control Register The Serial Data Buffer (SBUF) register is used to hold serial port input or output data depending on whether the serial port is receiving or transmitting data. PSW definition MSB LSB CY CY AC F0 RS1 RS0 OV P AC PSW.7 PSW.6 PSW.5 PSW.4 PSW.3 PSW.2 PSW.1 PSW.0 F0 RS1 RS0 OV - P Carry flag Auxiliary carry flag Flag 0 available to the user for general purpose Register bank selector bit 1. Register bank selector bit 0. Overflow flag Usable as a general purpose flag Parity flag. Set/clear by hardware at each instruction cycle to indicate an odd/ even number of "1" bus in the accumulator REGISTER BANK 0 1 2 3 ADDRESS 00H-07H 08H-0FH 10H-17H 18H-1FH RS1 0 0 1 1 RS0 0 1 0 1 Specifications subject to change without notice, contact your sales representatives for the most recent information. 8/27 PID256** 07/97 MOSEL VITELIC INC. Preliminary MV20556 Interrupt System A sophisticated multiple-source, two-priority-level, nested interrupt system is provided. The interrupt system is shown as below diagram. The interrupt request flag and program memory location of interrupt service program is shown in table on next page. Five interrupt sources Each interrupt can be individually enabled/disabled Enabled interrupts can be globally enabled/disabled Each interrupt can be assigned to either of two priority levels Each interrupt vectors to a separate location in program memory Interrupt nesting to two levels External interrupt requests can be programmmed to be level- or transition- activated Interrupt Overall External events and the real-time driven onchip peripherals require service by the CPU asynchronous to the execution of any particular section of code. To tie the asynchronous activities of these functions to normal program execution, a sophisticated multiple-source, two-priority-level, nested interrupt system is provided. Interrupt response latency ranges from 3s to 7s when using a 12 MHz crystal. The MV20556 acknowledges interrupt requests from five sources: Two from external sources via the #INT0 and INT1 pins, one from each of the two internal counters and one from the serial I/O port. Each interrupt vectors to a separate location in Program Memory for its service program. Each of the five sources can be assigned to either of two priority levels and can be independently enabled and disabled. Additionally all enabled sources can be globally disabled or enabled. Each external interrupt is programmable as either level- or transition-activated and is active-low to allow the "wire or-ing" of several interrupt sources to the input pin. The interrupt system is shown diagrammatically in below figure. Interrupt System Functional Description Interrupts result in a transfer of control to a new program location. The program servicing the request begins at this address. In the MV20556 there are five hardware sources that can generate an interrupt request. The starting address of the interrupt service program for each interrupt source is shown in table on next page. A resource requests an interrupt by setting its associated interrupt request flag in the TCON or SCON register, as detailed in following table. The interrupt request will be acknowledged if its interrupt enable bit in the Interrupt Enable register is set and if it is the highest priority resource requesting an interrupt. A resource's interrupt priority level is established as INTERRUPT PRIORITY REGISTER: IP.0 INPUT LEVEL AND INTERRUPT REQUEST FLAG REGISTER: TCON.1 SOURCE ENABLE IE.0 GLOBAL ENABLE IE.7 POLLING HARDWARE IE0 TCON.5 EX0 IE.1 PX0 IP.1 HIGH PRIORITY INTERRUPT REQUEST TF0 TCON.3 ET0 IE.2 PT0 IP.2 SOURCE I.D. VECTOR IE1 TCON.7 EX1 IE.3 PX1 IP.3 TF1 SCON.0 TI SCON.1 RX ET1 IE.4 PT1 IP.4 LOW PRIORITY INTERRUPT REQUEST ES EA PS SOURCE I.D. VECTOR Specifications subject to change without notice, contact your sales representatives for the most recent information. 9/27 PID256** 07/97 MOSEL VITELIC INC. Preliminary MV20556 Interrupt System(Cont'd) Interrupt System Functional Description (Cont'd) high or low by the polarity of a bit in the Interrupt Priority register. These bit assignments are shown in IP definition. Setting the resource's associated bit to a one (1) programs it to the higher level. The priority of multiple interrupt requests occurring simultaneously and assigned to the same priority level is also shown in below table. The servicing of a resources's interrupt request occurs at the end of the instruction-in-progress. The processor transfers control to the starting address of this resource's interrupt service program and begins execution. Within the Interrupt Enable register (IE) there are six addressable flags. Five flags enable/disable the five interrupt sources when set/cleared. Setting/clearing the sixth flag permits a global enable/disable of each enabled interrupt request. Setting/clearing a bit in the Interrupt Priority register (IP) establishes its associated interrupt request as a high/low priority (Table on next page). If a low-priority level interrupt is being serviced, a high-priority level interrupt will interrupt it. However, an interrupt source cannot interrupt a service program of the same or higher level. The processor records the active priority level(s) by setting internal flip-flop(s). One of these non-addressable flip-flops is set while a low-level interrupt is being serviced. The other flip-flop is set while the high-level interrupt is being serviced. The appropriate flip-flop is set when the processor transfers control to the service program. The flip-flop corresponding to the interrupt level being serviced is reset when the processor executes an RETI Instruction. To summarize, the sequence of events for an interrupt is: A resource provokes an interrupt by setting its associated interrupt request bit to let the processor know an interrupt condition has occurred. The CPU's internal hardware latches the interrupt request near the falling-edge of ALE internal signal in the tenth (10th), twenty-second (22nd), thirty-fourth (34th) and forty-six (46th) oscillator period of the instruction-in-progress. The interrupt request is conditioned by bits in the interrupt enable and interrupt priority registers. The processor acknowledges the interrupt by setting one of the two internal "priority-level active" flip-flops and performing a hardware subroutine call. The call pushes the PC (but not the PSW) onto the stack and, for most sources, clears the interrupt request flag. The service program is then executed. Control is returned to the main program when the RETI instruction is executed. The RETI instruction also clears one of the internal "priority-level active" flip-flops. Most interrupt request flags (IE0, IE1, TF0 and TF1) are cleared when the processor transfers control to the first instruction of the interrupt service program. The TI and RI interrupt request flags are the exceptions and must be cleared as part of the serial port's interrupt service program. The process whereby a high-level interrupt request interrupt a low-level interrupt service program is called nesting. In this case the address of the next instruction in the low-priority service program is pushed onto the stack, the stack pointer is incremented by two (2) and processor control is transferred to the Program Memory location of the first instruction of the high-level service program. The last instruction of the high-priority interrupt service program must be an RETI instruction. This instruction clears the high "priority-level-active" flip-flop. RETI also returns processor control to the next instruction of the low-level interrupt service program. Since the lower "priority-level-active" flip-flop has remained set, high priority interrupts are re-enable while further low priority interrupts remain disabled. Start address Decimal HEX 3 0003H 11 000Bh 19 0013H 27 001Bh 35 0023h Interrupt Source External Request 0 Internal timer 0/ counter 0 External request 1 Internal timer 1/ counter 1 Internal Serial Port (Xmit) Internal Serial Port (Rcvr) Request Flag IE0 TF0 IE1 TF1 TI RI Bit Location TCON.1 TCON.5 TCON.3 TCON.7 SCON.1 SCON.0 Priority Flags .0 (highest) .1 .2 .3 .4 (lowest) Interrupt flags & addresses Specifications subject to change without notice, contact your sales representatives for the most recent information. 10/27 PID256** 07/97 MOSEL VITELIC INC. Preliminary MV20556 Interrupt System(Cont'd) The highest-priority interrupt request gets serviced at the end of the instruction-in progress unless the request is made in the last fourteen oscillator periods of the instruction-in-progress. Under this circumstance, the next instruction will also execute before the interrupt's subroutine call is made. The first instruction of the service program will begin execution twenty-four oscillator periods (the time required for the hardware subroutine call) after the completion of the instruction-in-progress or, under the circumstances mentioned earlier, twenty-four oscillator periods after the next instruction. Thus, the greatest delay in response to an interrupt request is 86 oscillator periods (approximately 7sec @ 12 MHz). Examples of the best and worst case conditions are illustrated in right side table. External Interrupts The external interrupt request inputs (#INT0 and #INT1) can be programmed for either transitionactivated or level-activated operation. Control of the external interrupts is provided by the four low-order bits of TCON. When IT0 and IT1 are set to one (1), interrupt requests on #INT0 and #INT1 are transition-activated (high-to-low); or else they are low-level activated. IE0 and IE1 are the interrupt request flags. These flags are set when their corresponding interrupt request inputs at #INT0 and MSB #INT1, respectively, are low when sampled by the MV20556 and the transition activated scheme is selected by IT0 and IT1. When IT0 and IT1 are programmed for level-activated interrupts, the IE0 and IE1 flags are not affected by the inputs #INT0 and INT1, respectively. Transition-Activated Interrupts The external interrupt request inputs (#INT0 and #INT1) can be programmed for high-to-low transition-activated operation. For transition-activated operation, the input must remain low for greater than twelve oscillator periods, but need not be synchronous with the oscillator. It is internally latched by the MV20556 near the falling-edge of ALE during an instruction's tenth, twenty-second, thirty-fourth and forty-sixth oscillator periods and, if the input is low, IE0 or IE1 is set. The upward transition of a transition- activated input may occur at any time after the twelve oscillator period latching time, but the input must remain high for twelve oscillator periods before reactivation. Level-Activated Interrupt The external interrupt request inputs (#INT0 and #INT1)can be programmed for level-activated operation. The input is sampled by the MV20556 near the falling-edge of internal signal ALE during the instruction's tenth (10th), twenty-second (22nd), thirtyfourteen (34th) and forty-sixth (46th) oscillator periods. LSB EA EA IE.7 - - ES ET1 EX1 ET0 EX0 ES ET1 EX0 ET0 EX1 IE.6 IE.5 IE.4 IE.3 IE.2 IE.1 IE.0 Disable all interrupts. If EA=0, no interrupt will be acknowledged. If EA=1, each interrupt source is individually enabled or disabled by setting or clearing its enable bit. Cleared by software to disable all interrupts, independent of the state of IE. 4-IE.0 Reserve for future use. Reserve for future use. Enable Serial port control bit. Set/cleared by software to enable/disable interrupts from TI or RI flags. Enable or disable the timer 1 overflow interrupt. Set/cleared by software to enable/disable interrupts from timer/counter 1 Reserve for future use. Enable External interrupt 1 control bit. Set/cleared by software to enable/disable interrupts from INT1. Enable or disable the timer 0 overflow interrupt. Set/cleared by software to enable/disable interrupts from timer/counter 0 Enable External interrupt 0 control bit. Set/cleared by software to enable/disable interrupts from INT0 IE definition Specifications subject to change without notice, contact your sales representatives for the most recent information. 11/27 PID256** 07/97 MOSEL VITELIC INC. Preliminary MV20556 Interrupt System (Cont'd) that occurs fourteen oscillator periods before the end of the instruction in progress, an interrupt subroutine call is made. The level-activated input need be low only during the sampling that occurs fourteen oscillator periods before the end of the instruction-in-progress and may remain low during the entire execution of the service program. However, the input must be raised before the service program completes to avoid possible envoking a second interrupt. MSB LSB PS PT1 PX0 PT0 PX1 IP.7 IP.6 IP.5 IP.4 IP.3 IP.2 IP.1 IP.0 - - PS PT1 PX1 PT0 PX0 Reserve for future use. Reserve for future use. Reserve for future use. Serial Port Priority control bit. Set/cleared by software to specify high/low priority interrupts for Serial port. Defines the idle or power down mode interrupt priority level. Set/cleared by software to specify high/low priority interrupts for timer/counter1. External interrupt 1 Priority control bit. Set/cleared by software to specify high/low priority interrupts for INT1. Defines the timer 0 interrupt priority level. Set/cleared by software to specify high/low priority interrupts for timer/counter0. External interrupt 0 Priority control bit. Set/cleared by software to specify high/low priority interrupts for INT0. IP definition Specifications subject to change without notice, contact your sales representatives for the most recent information. 12/27 PID256** 07/97 MOSEL VITELIC INC. Preliminary MV20556 Timer/Counter Timer/Counter Overall The MV20556 contains two 16-bit counters for measuring time internals, measuring pulse widths, counting events and generating precise, periodic interrupt requests. Each can be programmed independently to operate as an 8048 8-bit timer with divide by 32 prescaler or as an 8-bit counter with divide by 32 prescaler (Mode 0), as a 16-bit time-interval or event counter (Mode 1), or as an 8-bit time-interval or event counter with automatic reload upon overflow (Mode 2). Additionally, counter 0 can be programmed to a mode that divides it into one 8-bit time-internal or event counter and one 8-bit time-interval counter (Mode 3). When counter 0 is in Mode 3, counter 1 can be programmed to any of the three aforementioned modes, although it cannot set an interrupt request flag or generate an interrupt. This mode is useful because counter 1's overflow can be used to pulse the serial port's transmission-rate generator. Along with their multiple operating modes and 16-bit precision, the counters can also handle very high input frequencies. These range from 3 MHz to 40 MHz (for 3 MHz to 40 MHz crystal) when programmed for an input that is a division by 12 of the oscillator frequency and from 0 Hz to an upper limit of 1 MHz (for 25 MHz crystal) when programmed for external inputs. Both internal and external inputs can be gated to the counter by a second external source for directly measuring pulse widths. The counters are started and stopped under software control. Each counter sets its interrupt request flag when it overflows from all ones to all zeros (or auto-reload value). The operating modes and input sources are summarized in right side Figures. counter. TH1 holds the reload value. TL1 is incremented. The value in TH1 is reload onto TL1 when TL1 overflows from all ones. Mode 3: Prevents incrementing of timer/counter When counter 1's mode is reprogrammed to mode 3 (from mode 0, 1 or 2), it disables the incrementing of crystal oscillator /12 TIMER 0 exteranl source 8 TH0 8 TL0 MODE 0: 8-bit timer/counter with prescaler MODE 1: 16-bit timer/counter MODE 2: 8-bit auto-reload timer/couner Overflow (Interrupt request) flag 0 crystal oscillator /12 TIMER 1 exteranl source 8 TH1 8 TL1 Overflow (Interrupt request) flag 1 pulse to serial port MODE 0: 8-bit timer/counter with prescaler MODE 1: 16-bit timer/counter MODE 2: 8-bit auto-reload timer/couner Mode 0, 1 and 2 crystal oscillator /12 exteranl source 8 TL0 8 TH0 Overflow (Interrupt request) flag 1 Counter 1/Timer 1 Counter 1/Timer 1 can be configured in one of four modes by software program code on the fly: Mode 0: 8-bit timer/counter with prescaler Provides an 8-bit counter with a divide-by-32 prescaler or an 8-bit timer with a divideby-32 prescaler. Mode 1: 16-bit timer/counter Configures counter 1 as a 16-bit timer/counter. Mode 2: 8-bit auto-reload timer/counter Configures counter 1 as an 8-bit auto-reload timer/ MODE 3: 8-bit timer/counter Overflow (Interrupt request) flag 0 crystal oscillator /12 TIMER 1 exteranl source 8 TH1 8 TL1 MODE 0: 8-bit timer/counter with prescaler MODE 1: 16-bit timer/counter MODE 2: 8-bit auto-reload timer/couner pulse to serial port Mode 3 13/27 PID256** 07/97 Specifications subject to change without notice, contact your sales representatives for the most recent information. MOSEL VITELIC INC. Preliminary MV20556 Timer/Counter (Cont'd) the counter. This mode is provided as an alternative to use TR1 bit (TCON.6) to start and stop counter 1. The serial port receives a pulse each time that counter 1 overflows. The standard UART modes divide this pulse rate to generate the transmission rate. mode 3: stop Counter 0/Timer 0 Counter 0/Timer 0 can also be configured in one of four modes software program code on the fly: Mode 0-2: Mode 0-2 are the same as those for counter 1. Mode 3: 8-bit timer/counter (TL1) In mode 3, the configuration of TH0 is not affected by the bits in TMOD or TCON. It is configured solely as an 8-bit timer that is enabled for incrementing by TCON's TR1 bit. Upon TH0's overflows, the TF1 flag gets set. Thus, neither TR1 nor TF1 is available to counter 1 when counter 0 is in mode 3. The function of TR1 can be done by placing counter 1 in mode 3, so only the function of TF1 is actually given up by counter 1. In mode 3, TL0 is configured as an 8-bit timer/counter and is controlled, as usual, by the GATE (TMOD.3), C/#T(TMOD.2), TR0 (TCON.4) and TF0 (TCON.5) control bits. MSB Configuring of Timer/Counter The use of the timer/counters is determined by two 8bit registers, TMOD (timer mode) and TCON (timer control). The input to the counter circuitry from an external reference (for use as a counter), or from the on-chip oscillator (for use as a counter), or from the onchip oscillator (for use as a timer), depending on whether TMOD's C/#T bit is set or cleared, respectively. When used as a timer base, the on-chip oscillator frequency is divided by twelve (12) before being input to the counter circuitry. When TMOD's Gate bit is set (1), the external reference input (T1, T0) or the oscillator input is gated to the counter conditional upon a second external input (#INT0, #INT1) being high. When the Gate bit is zero (0), the external reference or oscillator input is unconditionally enabled. In either case, the normal interrupt function of #INT0 and #INT1 is not affected by the counter's operation. If enabled, an interrupt will occur when the input at #INT0 or #INT1 is low. The counters are enabled for incrementing when TCON's TR1 and TR0 bits are set. When the counters overflow the TF1 and TF0 bits in TCON get set and interrupt requests are generated. The functions of the bits in TCON are shown in below table. The functions of the bits in TMOD are shown in table on next page. Operation The counter circuitry counts up to all 1's and then overflows to either 0's or the reload value. Upon overflow, TF1 or TF0 gets set. When an instruction LSB TF1 TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 TR1 TCON.7 TCON.6 TCON.5 TCON.4 TCON.3 TCON.2 TCON.1 TCON.0 TF0 TR0 - - IDF - Timer 1 overflow flag. Set by hardware when the timer/counter 1 overflows. Cleared by hardware as processor vectors to the interrupt service routine. Timer 1 run control bit. Set/cleared by software to turn timer/counter 1 ON/OFF. Timer 0 overflow flag. Set by hardware when the timer/counter 0 overflows. Cleared by hardware as processor vectors to the interrupt service routine. Timer 0 run control bit. Set/cleared by software to turn timer/counter 0 ON/OFF. Interrupt 1 edge flag. Set by hardware when external interrupt edge detected. Cleared when interrupt processed. Interrupt 1 Type control bit. Set/cleared by software to specify falling edge/low level triggered external interrupts. Interrupt 0 edge flag. Set by hardware when external interrupt edge detected. Cleared when interrupt processed. Interrupt 1 Type control bit. Set/cleared by software to specify falling edge/low level triggered external interrupts. TCON definition Specifications subject to change without notice, contact your sales representatives for the most recent information. 14/27 PID256** 07/97 MOSEL VITELIC INC. Preliminary MV20556 Timer/Counter (Cont'd) changes the timer's mode or alters its control bits, the actual change occurs at the end of the instruction's execution. The T1 and T0 inputs are sampled near the fallingedge of ALE in the tenth(10th), twenty-second(22nd), thirty-fourth(34th) and forty-sixth(46th) oscillator periods of the instruction-in-progress. They are also sampled in the twenty-second oscillator period of MOVX despite the absence of internal signal ALE. Thus, an external reference's high and low times must each be a minimum of twelve oscillator periods in duration. There is a twelve oscillator period delay from when a toggled input (transition from high to low) is sampled to when the counter is ineremented. Reading/Reloading The timer/counters can be read and reloaded on the fly. However, the 16-bit timer/counters must be read and loaded as two 8-bit bytes. During a read the potential "phasing error" can be programmed around, as follows: RTC MOV A, TH0 MOV B, TL0 CJNE A, TH0, RTC Timer 1 MSB Timer 0 LSB GATE GATE C/#T M1 M0 GATE C/#T M1 M0 C/#T M1 M0 M1 0 0 1 1 1 When TRx (in TCON) is set and GATE=1, TIMER/COUNTERx will run only while INTx pin is high (hardware control). When GATE=0, TIMER/COUNTERx will run only while TRx=1 (software control). Timer or counter selector. Cleared for timer operation (input from internal system clock). Set for counter operation (input form Tx input pin). Mode selector bit. Mode selector bit. M0 0 1 0 1 1 Operating mode Mode 0. (13-bit timer, by prescaled.) Mode 1. (16-bit timer/counter) Mode 2. (8-bit auto-load timer/counter) Mode 3. (TL0 is an 8-bit timer/counter controlled by the standard timer 0 control bits. TH0 is an 8-bit timer and is controlled by timer 1 control bits.) Mode 3. (Timer/counter 1 stopped). TMOD definition Specifications subject to change without notice, contact your sales representatives for the most recent information. 15/27 PID256** 07/97 MOSEL VITELIC INC. Preliminary MV20556 External Interface MV20556 Reset Processor initialization is accomplished with acitivation of the RES pin. To reset the processor, this pin should be held high for at least twenty-four oscillator periods. Upon powering up, RES should be held high for at least 1 ms after the power supply stabilizes to allow the oscillator to stabilize. Upon receipt of RES, the processor ceases instruction execution and remains dormant for the duration of the pulse. The pins assume their initialization states within 2 machine cycles clocks. The low-going transition then initiates a sequence which requires approximately twelve oscillator periods to execute before ALE(internal signal) is generated and normal operation commences with the instruction at absolute location 0000H. This sequence ends with registers initialized as shown in right table. When the processor is reset all ports are immediately written with ones (1's). The Schimitt-trigger input has a small internal pull down resistor which permits power-on reset (as shown in right to Figure) using only a small capacitor tied to VDD. A conventional external reset circuit, such as that in right Figure, can also be used. I OL Output low current. For port 1 and port 3, MV20556 provided I OL up to 18mA per pin typicallly at VOL=0.45V. User are free to choose any one of these 15 pins to perform this high current sink capability. But they are restricted: no more than 80 mA I OLs for all output pins. 30F RES R RES Power-on Reset 1K ohm RES MV20556 RRES MV20556 1K ohm 30F RES RRES External Reset Register PC SP PSW DPH, DPL A, B Content after Content after Reset at Power on Reset while running 0000H 07H 00H 00H 00H 0000H 07H 00H 00H 00H E0H or 00H 60H or 00H 00H 00H 00H 00H 00H indeterminate FFH (*1) unchanged IP E0H or 00H IE 60H or 00H SCON 00H TMOD 00H TCON 00H TH1, TH0 00H TL1, TL0 00H SBUF indeterminate Port 1 & 3 FFH (*1) Internal RAM indeterminate *1 configures all i/o pins as inputs Register vs Reset Specifications subject to change without notice, contact your sales representatives for the most recent information. 16/27 PID256** 07/97 MOSEL VITELIC INC. Preliminary MV20556 External Interface (Cont'd) Idle Mode During idle mode, the CPU is stopped but below blocks are kept functioning:clock generator, RAM, timer/ counters, serial port and interrupt block. During idle mode, the CPU is stopped but below blocks are kept functioning: clock generator, RAM, timer/ counters, serial port and interrupt block. To save power consumption, user's software program can invoke this mode. The on-chip data RAM retains the values during this mode, but the processor stops executing instructions. In Idle mode (IDL=1), the oscillator continues to run and the interrput, and timer blocks continue to be clocked but the clock signal is gated off to the CPU. The activities of the CPU no longer exist unless waiting for an interrupt request. -An instruction that sets flag (PCON.0) causes that to be the last instruction executed before going into the Idle Mode. -In the Idle Mode, the internal clock signal is gated off to the CPU, but not to the interrupt, Timer function. -The CPU status is entirely preserved in its: the Stack Pointer, Program Counter, Program Status Word, Accumulator, and all other registers maintain their data during Idle mode. -There are two ways to terminate the Idle Mode. 1) By interrupt Activation of any enabled interrupt will cause flag (PCON.0) to be cleared by hardware, termination the Idle Mode. After the program wakes up, the PC value will point as interrupt vector (if enable IE register) and execute interrupt service routine then return to PC+1 address after the program wakes up. 2) By hardware reset Since the clock oscillator is still running, the hardware reset needs to be held active for only two machine cycles (24 clocks) to complete the reset. All SFR and PC value will be cleared to reset value. After the program wakes up, the PC value will be 0023h (if enable IE register) and execute interrupt service Vdd routine and then returns to PC+1 address after the program wakes up. Power Down Mode It saves the RAM content, stops the clock generator and disables every other blocks' function until the coming hardware reset. To save even more power consumption, user's software program can invoke this mode. The SFRs and the on-chip data RAM retain their values during this mode, but the porcessor stops executing instructions. In Power-Down mode (PD=1) the oscillator is frozen. -An instruction that sets flag (PCON.1) causes that to be the last instruction executed before going into the Power Down Mode. -In the Power Down Mode, the on-chip oscillator is stopped. With the clock frozen, all functions are stopped, but the on-chip RAM and Special Function Registers are held. -Reset redefines all the SFRs, but does not change the on-chip RAM. -There is only one way to terminate the Power Down Mode - by hardware reset. All SFR and PC value will be cleared to reset value. After the program wakes up, the PC value will be 0023h (if enable IE register) and execute interrupt service routine and then returns to PC+1 address after the program wakes up. -Care must be taken, however, to ensure that Vdd is not reduced before the Power Down Mode is invoked, and that Vdd is restored to its normal operating level before the Power Down Mode is terminated. -The hardware reset must be held active long enough to allow the oscillator to restart and stabilize. Data can be maintained valid in the Internal Data RAM while the remainder of the MV20556 is powered down. When powered down, the MV20556 consumes about 10% of normal operating power. During normal operation both the CPU and the internal RAM derive their power from VDD. However, the internal RAM will derive its power from RES when the voltage on VDD is more than a diode drop below that on RES. When a power-supply failure is imminent, the user's system generates a "power-failure" signal to interrupt the Mode Normal Operation #INTx (power fail) Interrupt RES Normal Operation service routine Program memory Internal Internal Port 3 Data Data Idle Power Down Specifications subject to change without notice, contact your sales representatives for the most recent information. 17/27 PID256** 07/97 MOSEL VITELIC INC. Preliminary MV20556 External Interface (Cont'd) processor via #INT0 or #INT1. This power-failure signal must be early enough to allow the MV20556 before VDD falls below its operating limit. The program servicing the power-failure interrupt request must save any important data and machine status into Internal Data RAM. The service program must also enable the backup power supply to the RES pin. Applying power to the RES pin resets the MV20556 and retains the internal RAM data valid as the VDD power supply falls below limit. Normal operation resumes when RES is returned low. Figure on last page left column shows the waveforms for the power-down sequence. Timing Generation Timing generation for the MV20556 completely selfcontained, except for the frequency reference which can be a crystal or external clock source. The on-board oscillator is a parallel anti-resonant circuit with a frequency range of 3 M to 40 MHz. The XTAL2 pin is the output of a high-gain amplifier, while XTAL1 is its input. A crystal connedted between XTAL1 and XTAL2 provides the feedback and phase shift required for oscillation. The 3 to 40 MHz range is also accomodated when an external TTL compatible clock is applied to XTAL1 as the frequency source. The I/O Circuit WRENB DB RES RDENB LQ D SD Pn P1, P3 Specifications subject to change without notice, contact your sales representatives for the most recent information. 18/27 PID256** 07/97 MOSEL VITELIC INC. Preliminary MV20556 Absolute Maximal Rating Symbol VDD - Vss VIN VOUT Name DC supply Voltage Input voltage output voltage Rating -0.5 - +7.0 Vss-0.3 - VDD+0.3 Vss - VDD 0 - +70 -55 - +125 Unit V V C C T(Operating) Operating Temperature Storage Temperature T(Storage) * Note: Operation beyond Absolute Maximal Rating can adversely affect device reliability. Operating Conditions Symbol TA Vdd fosc 16 fosc 25 fosc 40 Description Ambient temperature under bias Supply voltage Oscillator Frequency of MV20556C16 Oscillator Frequency of MV20556C25 Oscillator Frequency of MV20556C40 Min. 0 4.5 3 3 3 Typ. 25 5.0 16 25 40 Max 70 5.5 16 25 40 Unit Test Condition C V Vss=0V MHz MHz MHz DC Characteristics (16 MHz, typical operating conditions) Symbol VIL VIH VIH1 VOH I IL I TL I LI I OL I OL1+3 R RES C IO I CC Parameter Input Low Voltage Input High Voltage Input High Voltage Output High Voltage Logical 0 Input Cruuent Logical 1 To 0 Transition Current Input Leakage Current Output Low Current Output low current of 15 pins Reset Pulldown R Pin Capacitance Power Supply Current Valid * note 2 XTAL, RES Port 1,3 Ports 1,3 Ports 1,3 Port 1 Port 1,3 Port 1 & 3 Min. -0.5 0.2Vc+0.9 0.7Vcc 2.4 0.9Vcc Typ. Max 0.2Vcc-0.1 Vcc+0.5 Vcc+0.5 -50 -650 10 18 50 80 150 10 8 5 1 Vdd Vdd Vdd 5 3 Unit V V V V V uA uA uA mA mA Kohm pF mA mA uA Test Conditions IOH=-60uA IOH=-10uA Vin=0.45V Vin=2V 0.45 Note 2:=Except XTAL, RES DC Characteristics at 25 MHz to be available DC Characteristics at 40 MHz to be available Specifications subject to change without notice, contact your sales representatives for the most recent information. 19/27 PID256** 07/97 MOSEL VITELIC INC. Preliminary MV20556 AC Characteristics (16 MHz, typical operating conditions) Symbol Parameter Valid Cycle Min. Typ. Max Unit nS nS nS nS Remarks T CHCL Clock fall time T CLCX Clock low time T CLCH Clock rise time T CHCX Clock high time T CLCL Clock period 62 T SCLK serial port clock cycle T QVCH Output data Setup to clock rise T CHQX Output data hold after clock rise T CHDV Clock rise to input data valid T CHDX Input data hold after clock rise T POR Power On reset time T WAKE Oscillator wake up time Reset pulse width T RES nS uS nS nS nS nS nS nS uS Power on Power Down Mode Running 1.5 24* T CLCH AC Characteristics (25 MHz, typical operating conditions) Symbol T CHCL T CLCX T CLCH T CHCX T CLCL T SCLK T QVCH T CHQX T CHDV T CHDX T POR T WAKE T RES Parameter Clock fall time Clock low time Clock rise time Clock high time Clock period serial port clock cycle Output data Setup to clock rise Output data hold after clock rise clock rise to input data valid Input data hold after clock rise Power On reset time Oscillator wake up time Reset pulse width Valid Cycle Min. Typ. Max 40 Power on Power Down Mode Running 960 Unit nS nS nS nS nS uS nS nS nS nS nS nS nS Remarks 24* T CLCH Specifications subject to change without notice, contact your sales representatives for the most recent information. 20/27 PID256** 07/97 MOSEL VITELIC INC. Preliminary MV20556 AC Characteristics (40 MHz, typical operating conditions) Symbol Parameter Valid Cycle Min. Typ. Max Unit nS nS nS nS Remarks T CHCL Clock fall time T CLCX Clock low time T CLCH Clock rise time T CHCX Clock high time T CLCL Clock period 25 T SCLK serial port clock cycle T QVCH Output data Setup to clock rise T CHQX Output data hold after clock rise T CHDV clock rise to input data valid T CHDX Input data hold after clock rise T POR Power On reset time T WAKE Oscillator wake up time Reset pulse width T RES nS uS nS nS nS nS nS nS nS Power on Power Down Mode Running 600 24* T CLCH Application Reference X'tal 3 MHz C1 C2 R 39 pF 39 pF open 6 MHz 16 MHz 39 pF 39 pF open 30 pF 30 pF open 25 MHz 15 pF 15 pF 62 Kohm 40 MHz 5 pF 5 pF 4700 ohm X'tal R X2 C1 C2 MV20556 X1 Specifications subject to change without notice, contact your sales representatives for the most recent information. 21/27 PID256** 07/97 MOSEL VITELIC INC. Preliminary MV20556 Emulation Board Model number: M9257 Two layers There is a 74373 chip soldered under chip 27C512 The 4 KB program code should be programmed into the first 4 KB address location of EPROM 27C512-150 which is inserted into U4 location. When applying at different working clock, this M9257 demands different speed of EPROM chip 16 MHz: 27C512-200 or faster 25 MHz: 27C512-100 or faster 40 MHz: 27C512-60 or faster 0 1 2 cm TOP VIEW 28 15 27C512-mm U4 40 21 MSU2031Cnn U1 20 PROFILE Timing Critical, Requirement of External Clock Vdd-0.5V 70%Vdd (Vss=0.0V is assumed) T CLCL 0.45V 20%Vdd-0.1V T CHCX T CLCX T CHCL T CLCH Specifications subject to change without notice, contact your sales representatives for the most recent information. 22/27 PID256** 07/97 MOSEL VITELIC INC. Preliminary MV20556 20L 300mil PDIP Information D S E E1 A1 A2 A C L e1 eA B1 B \ Note: 1.Dimension D Max & S include mold flash or tie bar burrs. 2.Dimension E1 does not include interlead flash. 3.Dimenseion D & E1 include mold mismatch and are determined at the mold parting line. 4.Dimension B1 does not include dambar protrusion/ infrusion. 5.Controlling dimension is inch. 6.General appearance spec. should base on final visual inspection spec. Symbol A A1 A2 B B1 C D E E1 e1 L \ eA S Dimension Inch minimal/maximal - / 0.175 0.010 / 0.125 / 0.135 0.016 / 0.022 0.058 / 0.064 0.008 / 0.014 - / 1.040 0.290 / 0.310 0.245 / 0.255 0.090 / 0.110 0.120 / 0.140 0 / 15 0.335 / 0.375 - / 0.075 Dimension in mm minimal/maximal - / 4.45 0.25 / 3.18 / 3.43 0.41 / 0.56 1.47 / 1.63 0.20 / 0.36 - / 26.42 7.37 / 7.87 6.22 / 6.48 2.29 / 2.79 3.05 / 3.58 0 / 15 8.51 / 9.53 - / 1.91 Specifications subject to change without notice, contact your sales representatives for the most recent information. 23/27 PID256** 07/97 MOSEL VITELIC INC. Preliminary MV20556 20L Small Outline Gull Wing Package 01 C L L1 R1 E H A1 A2 G 03 R2 A 0 D 01 Y B Note: 1. Dimension D does not include mold flash, protrustions or gate burrs. Allowance protrusion is 0.25mm per side. Dimensions E does not include inter-lead flash or protrusions. Symbol A A1 A2 B C D E e G H L L1 R1 R2 0 01 03 C Dimension in Inch minimal/maximal - / 0.100 0.004 / 0.012 0.091 0.013 / 0.020 0.007 / 0.011 0.496 / 0.508 0.291 / 0.299 0.050 0.020 x 45 0.394 / 0.419 0.015 / 0.050 Dimension in mm minimal/maximal 2.36 / 2.64 0.10 / 0.30 2.31 0.33 / 0.51 0.18 / 0.21 12.60 / 12.94 7.39 / 7.51 1.27 10.01 / 10.64 0.38 / 1.21 0/8 7 REF 7 REF 0.004 as left as left as left 0.10 Specifications subject to change without notice, contact your sales representatives for the most recent information. 24/27 PID256** 07/97 MOSEL VITELIC INC. Preliminary MV20556 PAD-NAME VSSGND VSSGND VSSGND NC P3.7 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 X-COORD 1536 1385 1234 1037 816 595 374 168 168 168 168 168 Y-COORD 2244 2244 2244 2244 2244 2244 2244 1906 1678 1453 1226 1001 Bonding Information Index 1 2 3 4 5 6 7 8 9 10 11 12 PAD-NAME P0.7 VDD VDD RES RxD / P3.0 TxD / P3.1 XTAL2 XTAL1 #INT0 / P3.2 #INT1 / P3.3 T0 / P3.4 T1 / P3.5 X-COORD 540 738 889 1085 1306 1527 1934 1934 1934 1934 1934 1735 Y-COORD 168 168 168 168 168 168 632 954 1186 1413 1638 2244 Index 13 14 15 16 17 18 19 20 21 22 23 24 Logo 19 20 18 17 16 15 14 13 12 21 MV20556 22 2200 x 3160 (m) PAD SIZE : 90 x 90 (m) 23 substrate should be bonded to Vss (Gnd) 11 10 9 8 24 7 pid 256* 11/96 (6) pid 256** 07/97 (27) 1 2 3 4 5 6 Taiwan #1 Creation Road I, Science - based Industrial Park, Hsinchu, 30077 Taiwan, ROC "audio_reply@mosel.com.tw" TEL: 886-3-577-0055 FAX: 886-3-577-2788 FAX: 886-3-578-4732 Mdm: 886-3-578-0493 http:\\www.moselvitelic.com Taipei 7F, #102 Section 3, Ming Chung E. Road, Taipei,105 Taiwan, ROC TEL: 886-2-545-1213 FAX: 886-2-545-1214 Mdm: 886-2-545-1464 China (Vitelic HKG ShenZhen) Room #209 San Da building, #19 ZhenHua Road, Futian, ShenZhen city, P.R.China TEL: 86-755-334-5766 FAX: 86-755-332-3995 Mdm: 86-755-332-3995 Hongkong #19 Dai Fu Street, Taipo Industrial Estate, Taipo, N.T. Hongkong TEL: 852-2388-8277(MKO) TEL: 852-2665-4883 FAX: 852-2664-2406 FAX: 852-2770-8011(MKO) Mdm: 852-2388-0244 U.S.A. #3910 North First Street, San Jose, CA. 65134-1501 U.S.A. TEL: 1-408-433-6000 FAX: 1-408-433-0952 Japan Room 302, Annex-G, Higashi-Nakano, Nakano-Ku, Tokyo 164 Japan TEL: 81-3-3365-2851 FAX: 81-3-3365-2836 Specifications subject to change without notice, contact your sales representatives for the most recent information. 25/27 PID256** 07/97 MOSEL VITELIC INC. Preliminary MV20556 3-digit production code filled by MVI only Mosel Vitelic Inc. 886-3-5772788 Attn: Sales & Marketing Department To: Product Request Form We hereby request MVI to start producing MV20556 which is specified below . Please send us the product code and a hardcopy of data code as well as data code file duplicated on floppy diskette. No further confirmation is necessary. Production will start automatically once you receive our data code and verify that the checksum is match. Mass Production of the captioned device shall be done in accordance with the purchase order(s) issued by us or a company specified by us. All terms and conditions are based on the development agreement and/or contract signed between MVI and us. Data Code Descriptions Code Length File Length File Name Checksum Unused Data Byte Format h 00h filled FFh filled HEX format Binary code format EPROM 8751 chip File on Floppy E-mail file Top Marking (fill only for packaged) Use MVI logo, date code and part number Use my specifications as described below Specify below fields only for customer top marking Date code location descriptions Use regular date code as MVI's Leave it as blank use right side five letters Logo Specifications Leave it blank Use my specifications as attachment Part number specified, less than 15 digits Dice form 20L-PDIP IC descriptions 20L-SOP 16 MHz 25 MHz 40 MHz Media Phone # : Company Name : Signature : Name (Typed) : Position Title : Department, Section : Signature Date : Fax # : Specifications subject to change without notice, contact your sales representatives for the most recent information. 26/27 PID256** 07/97 MOSEL VITELIC INC. Preliminary MV20556 Mosel Vitelic Inc. 886-3-5772788 Attn: Sales & Marketing Department To: Logo Top Marking Request & spec. We hereby request MVI to have our logo printed on top of the device package. Below is the specification of our logo in 20:1 scale base. This logo diagram is clear enough and is able to be shrunk directly to fit into available top marking area described on page. Phone # : Company Name : Signature : Name (Typed) : Position Title : Department, Section : Signature Date : Fax # : Specifications subject to change without notice, contact your sales representatives for the most recent information. 27/27 PID256** 07/97 |
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